This article studies the asymptotic attractor of fourth-order reaction-diffusion equation u_t+αu_(x~4)+u_(x~2)+u~3-u=0 by constructing a solution sequence.
研究了四阶反应扩散方程ut+αux4+ux2+u3-u=0的渐近吸引子,即构造了一个有限维解序列。
The author studied the asymptotic attractor of fourth order nonlinear parabolic equations ut+σux4+αu+uux=f(x)by constructing a solution sequence.
考虑了四阶非线性抛物方程ut+σux4+αu+uux=f(x)的渐近吸引子,即构造了一个有限维解序列。
A solution sequence is constructed by using orthogonal decomposition,which approaches to the global attractor of the equation in long time,and the dimentional estimation of the asymptotic attractor is given.
研究周期边界条件下Navier-Stokes方程的长时间行为,利用正交分解法构造一个有限维解序列,证明了该解序列在长时间后无限逼近方程的整体吸引子,并且给出渐近吸引子的维数估计。
The resulting sequence will usually converge.
解序列一般说是收敛的。
Method for Solving PDE Numerically by Using Delta-sequence;
数值求解PDE的DELTA序列方法
Study on Cloning LEA Gene with the Function of Standing Against to Water Stress and Sequence Analysis;
抗旱基因LEA的克隆及其序列解析
Analyzing Unit Root Spurious Test;
单位根“伪检验”解析——以GDP时间序列为例
The Resolution of Magic Square by Means of Full Permutation and Recursion--C++ Programe Design;
用全排列和递归求解“魔方”——C++程序设计
A Simple Solution to Convolution Integral of Discrete Causal Series;
离散因果序列卷积和的一种简便解法
Singular-value Decomposition in Time Series Analysis
奇异值分解在时间序列分析中的应用
FPGA implementation of the despreading module in direct-sequence spread-spectrum system
直接序列扩频系统解扩模块FPGA实现
%9 could not retrieve the list of custom resolvers.
%9 无法获取自定义的冲突解决解决程序的列表。
isometric DNA sequence
同组异序ＤＮＡ序列
flanking sequence
侧翼序列，旁侧序列
serial anticipation method
序列预测法 序列预度法
targeting sequencing
前导序列，导向序列
The column information specified for the '%1' resolver is either missing or incorrect.
为“%1”冲突解决程序指定的列信息丢失或不正确。
Cannot resolve collation conflict for column %d in %ls statement.
无法解决列 %1!（在 %2! 语句中）的排序规则冲突。
The request failed validation because the server was unable to de-serialize the message.
请求验证失败，因为服务器不能解除消息序列化。
What is the suitable priority about the problem?
在情境判断中排列解决问题的优先顺序是什么？
The parallel form of the input sequence is decoded by means of a logical decoding circuit.
此并行形式序列通过逻辑解码电路输入。